USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP In 12nm, 16nm And 22nm Process Nodes For Immediate Licensing

Posted February 7, 2022 by mansisri

USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP In 12nm, 16nm And 22nm Process Nodes With Simple Integration And Flexible Customization Is Ready For Immediate Licensing For Your Advanced SoC Design!!

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP with matching Controller Cores which is silicon proven and in mass production with full certification and boasts high speed and low power interlink.

USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP in 12nm, 16nm and 22nm is a high performance SerDes IP designed for chips that perform high bandwidth data communication while operating at low power consumption. The Combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.

The Combo PHY support SATA3(6.0Gbps), USB3.0(5Gbps) and PCIe3(8.0Gbps) which is backward compatible with 1.5Gbps, 3.0Gbps for SATA and 2.5Gbps, 5Gbps for PCIe. With PIPE4 interface specification compatibility a 20bit/16bit selectable parallel data bus is implemented. Independent channel power down control, programmable transmit amplitude and FFE makes the IP highly controllable along with implemented Receiver equalization Adaptive-CTLE and DFE to compensate insertion loss. Production test support in the IP is optimized through high coverage at-speed BIST and loopback. Integrated on-die termination resistors and IO Pads/Bumps along with support for receiver detection, LFPS/OOB/Beacon signal generation & detection and Embedded Primary & Secondary ESD Protection makes it a highly reliable Combo PHY IP.

USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP Core in 12nm, 16nm and 22nm process technology along with MAC Controllers IP Cores are available independently or pre-integrated as a fully validated and integrated solution. The IP have been used in semiconductor industry’s Cellular Electronics, PC, Data storage (SSDs), Multimedia Devices and other Consumer Electronic products worldwide.

In addition to USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, T2M ‘s broad silicon Interface IP Core Portfolio includes standalone USB, PCIe, Serial ATA, HDMI, Display Port, MIPI, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, SD/eMMC and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo:

About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit:
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Issued By T2M-UG
Phone 9923060006
Business Address Munich
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Categories Semiconductors , Technology , Wireless
Tags chipsets , interface ips , ipcores , semiconductors , socs
Last Updated February 7, 2022